From Jose Pablo Pinilla and Alfredo Gualdrón of the Universidad Pontificia Bolivariana Colombia, we have a new paper featuring research based on realizing a configurable platform for emulation of different computer architectures, known as XISCKER (Reduced and Complex Instruction Set Computing Key Educational Resources).
This is a project planned to illustrate the structure and operational foundations of Central Processing Units, through the implementation of a configurable system with two processors, one RISC (Reduced Instruction Set Computing) and one CISC (Complex Instruction Set Computing), on an FPGA (Field Programmable Gate Array), along with a programming and monitoring user interface software.
Computer Architecture embraces all three aspects of a processor design: instruction set, functional estructure and hardware implementation. The main architectures are RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) which led to x86 as we still recognize now. Both designs bring electronics or computer science students the basic concepts they should learn.
Therefore, this project brings an opportunity to learn this basic concepts through the HDL description in Verilog of two processors (One for each architecture) implemented on FPGA devices (Xilinx and Altera), together with strong documentation, common assembly language instructions and support software.
A RISC processor instruction set and organization is designed so that it represents this architecture’s characteristics, such as: A large amount of registers, few Instructions of the same width and logical-arithmetic operations only between registers.
This processor’s structure is similar to the Multi-cycle MIPS described by Patterson and Hennessy  in order to facilitate the change between this system and a commercial MIPS-based processor in terms of code compatibility and structural behavior.
This CISC processor is based on the instruction set of the Motorola (now Freescale) HC08 and HC11 series which symbolizes the characteristics of CISC Architecture, with features like: Small set of registers with specific purposes, several addressing modes and therefore a large amount of instructions with different widths. Figure 3 contains a diagram that represents the main units and signals of this processor.
The X-ISCKER platform delivers the Verilog HDL description of two processors, an IDE software and the documentation that will allow new learners to familiarize with computer architecture foundations, and computer designers to come up with custom embedded processor solutions to their applications.
For more information and source code, please visit http://semilleroadt.upbbga.edu.co/xiscker.